Building up computer architecture from bits and gates to pipelines, caches, out-of-order execution, and accelerators — connecting every layer back to the code you write.
Lesson 1 of the Computer Architecture From First Principles series, expanded into a full worked-example treatment of the software/ISA/microarchitecture stack, the state-transformation model of a CPU, and how bits become unsigned integers, hex, and two's complement signed integers.
A ground-up derivation of the 32-bit ALU — from NOT/AND/OR/XOR truth tables through half and full adders, propagation delay, two's-complement subtraction, and multiplexer-based operation select, ending in a hand-traced 4-bit ALU.
Lesson 1, Part 3: how feedback turns a circuit into memory, why a CPU needs a clock at all, and the difference between a 3 GHz clock and 3 billion instructions per second — with the setup/hold time and critical-path math that actually sets a chip's maximum frequency.
How individual flip-flops become named, addressable storage: N-bit registers, the multi-port register file that lets one instruction read two operands and write a third in a single cycle, and the Program Counter as the special register that drives instruction sequencing.
Lesson 1, Part 5: how a fixed-width instruction becomes bits in memory, how a decoder splits those bits into fields for free, and how a control unit turns an opcode into the RegWrite, ALUSrc, MemRead, MemWrite, and Branch signals that drive the datapath — plus hardwired versus microcoded control.
Every piece built so far — PC, register file, ALU, control unit — finally moves together. This post traces ADD, LOAD, STORE, and BEQ cycle by cycle, wire by wire, and shows why the same ALU that adds two numbers is also the circuit computing every memory address and evaluating every branch.
A deep dive into why CPUs pipeline instructions, the data/control/structural hazards that pipelining creates, how forwarding and stalling fix them (and why load-use hazards can't be fully forwarded away), and how out-of-order execution — reservation stations, register renaming, and the reorder buffer — extracts instruction-level parallelism while still looking sequential from the outside.
A first-principles derivation of the cache address breakdown, replacement and write policies, multi-level page tables, and the roofline model — the memory-systems chapter that connects directly to real kernel and edge-AI work.
Why the instruction set is a hardware/software contract rather than an implementation, why x86 secretly runs a RISC engine under the hood, and how a compiler walks C++ down to bits through IR — the same layer LLVM and MLIR live at.
The closing chapter of Lesson 1: SIMD and Amdahl's Law worked from first principles, a full seven-question teardown of a 2-bit branch predictor, and the unified mental model tying number representation all the way to transistors — before Lesson 2 begins building a real CPU.
Opening Lesson 2, we design the instruction encoding for a real single-cycle CPU from scratch — deriving every field width from first principles and hand-encoding three real instructions down to actual 32-bit binary and hex.
Wiring the PC, register file, ALU, sign-extend unit, and data memory into one complete single-cycle datapath for a 7-instruction MIPS-style CPU — with every mux's job spelled out and a full labeled ASCII diagram as the centerpiece.
Deriving the complete control-signal truth table for a MIPS-style single-cycle CPU from first principles, and the two-level ALUOp/funct decoding scheme that lets a 2-bit main control signal and a small secondary decoder together select the correct ALU operation.
The Lesson 2 payoff: we hand-trace all seven instructions of a real program through the single-cycle datapath, one clock cycle at a time — every control signal, every register read, every ALU operation, every memory access, verified against hand-computed arithmetic.
The closing chapter of Lesson 2: applying the critical-path clocking math from Lesson 1 to the actual CPU we built, showing exactly how much clock period gets wasted on every non-LOAD instruction — and why that's the whole reason multi-cycle and pipelined designs exist.